🚀 go-pugleaf

In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes:
>
>I've been working on a project designing a processor with FPGA's.  One severe
>limitation I found is that their cells do not have tri-state outputs and thus
>forcing me to use MUXes on buses consuming a lot of the resources.
>
>Does anybody have any idea why they didn't make these cell outputs tri-state?
>
>Thanks.
>Pichet Chintrakulchai		(pichet@dartmouth.edu)


You don't say which FPGA you are using but the Xilinx 4000 series does
contain tristate buffers for just the kind of purpose you describe.
The buffers are not on each CLB but adjacent.  There are some
limitations as to where the buffers can connect up.  I have found
designs where the functionallity did _not_ work for a given device (due
to the size of the FPGA, size of my design, and the tristate buffer/bus
resources) but a larger chip probably would have.  In many other
designs I have not used any tristate logic (so I'm glad the CLBs aren't
all tristate by default).

Xilinx Technical Support; 1-800-255-7778.  (I'm not sure if they'll
talk to you on this number or whether this is just for people
with support contracts but it would be a good place to start.)

Craig

P.S. I have no connection with Xilinx other than being a user of
there products.  I have both good and bad things to say about their
stuff.

*** The opinions expressed are my own and do not necessarily reflect 
*** those of any other land dwelling mammals....

"The problem ain't what we don't know; it's what we know that just ain't so
Either we take familiar things so much for granted that we never think about 
how they originated, or we "know" too much about them to investigate closely."
-----------------
Craig F. Reese                           Email: cfreese@super.org
Institute for Defense Analyses/
Supercomputing Research Center 
17100 Science Dr.
Bowie, MD  20715-4300