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Article #683Re: Why no tri-state outputs in FPGA cells?
From: John Snow
Date: Wed, 16 Dec 1992 19:13
Date: Wed, 16 Dec 1992 19:13
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pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes: >Hello, >I've been working on a project designing a processor with FPGA's. One severe >limitation I found is that their cells do not have tri-state outputs and thus >forcing me to use MUXes on buses consuming a lot of the resources. >Does anybody have any idea why they didn't make these cell outputs tri-state? >Thanks. >Pichet Chintrakulchai (pichet@dartmouth.edu) Xilinx FPGAs do have tri-state buffers that can be used to create buses or to do wired-OR type logic. --John -- ----------------------------------------------------------------------------- John F. Snow jsnow@moons.sim.es.com Evans & Sutherland Computer Corp. Salt Lake City, Utah (801) 582-5847
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Newsgroups: comp.lsi.cad,comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!orca!javelin.sim.es.com!moons!jsnow From: jsnow@moons.sim.es.com (John Snow) Subject: Re: Why no tri-state outputs in FPGA cells? Message-ID: <BzD9Ez.7Gs@javelin.sim.es.com> Sender: news@javelin.sim.es.com Organization: Evans & Sutherland Computer Corp. References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> Date: Wed, 16 Dec 1992 19:13:47 GMT Lines: 22