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Article #684Re: Why no tri-state outputs in FPGA cells?
From: Philip Freidin
Date: Wed, 16 Dec 1992 18:43
Date: Wed, 16 Dec 1992 18:43
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In article <1992Dec14.221541.25270@dartvax.dartmouth.edu> pichet@coos.dartmouth.edu (Pichet Chintrakulchai) writes: >Hello, > >I've been working on a project designing a processor with FPGA's. One severe >limitation I found is that their cells do not have tri-state outputs and thus >forcing me to use MUXes on buses consuming a lot of the resources. > >Does anybody have any idea why they didn't make these cell outputs tri-state? > >Thanks. >Pichet Chintrakulchai (pichet@dartmouth.edu) -- Philip Freidin: Product Planning Manager, Xilinx, INC (rest of clever .sig still under construction.... coming to a terminal near you, Real Soon Now (tm))
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Newsgroups: comp.lsi.cad,comp.arch Path: arc1-ca.pugleaf.net!sparky!uunet!psinntp!xilinx!philip From: philip@xilinx.com (Philip Freidin) Subject: Re: Why no tri-state outputs in FPGA cells? Message-ID: <1992Dec16.184340.26605@xilinx.com> Sender: usenet@xilinx.com Organization: Xilinx Inc. References: <1992Dec14.221541.25270@dartvax.dartmouth.edu> Date: Wed, 16 Dec 1992 18:43:40 GMT Lines: 18