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Article #940

Re: Help wanted - Cadence Edge and EDIF

#940
From: Carly Wong
Date: Thu, 07 May 1992 01:31
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In article <dfs.705083429@sarek> dfs@doe.carleton.ca (David F. Skoll) writes:
>The problem is that these programs seem to be broken.  I took a
>standard-cell xnor, exported it with 'edifout', imported it with
>'edifin', and the result was a very different cell.  In particular,
>'edifin' has problems with portImplementation constructs, always
>converting the layer to 'wire' when the port is really on the 'dmet'
>layer.
>
>Has anyone successfully used edifin and edifout?  If so, how?

I have encountered the same problems.  The pins of a standard cell layout
are not recognized once read into Cadence.    There's problems with other
terminals too, such as jumpers.   Other layers such as PRBoundary are not
recognized as well. 

I suspect those are bugs with edifin/out.
I got around that by writing a SKILL program to fix the read in layouts,
such as search for "wire" layers, and replace with "dmet".
I could send you the program if you are interested.
 
Carly Wong
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From: carlyw@ee.ubc.ca (Carly Wong)
Subject: Re: Help wanted - Cadence Edge and EDIF
Message-ID: <1992May7.013138.1152@ee.ubc.ca>
Organization: University of BC, Electrical Engineering
References: <dfs.705083429@sarek>
Date: Thu, 7 May 1992 01:31:38 GMT
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