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Article #940Re: Help wanted - Cadence Edge and EDIF
From: Carly Wong
Date: Thu, 07 May 1992 01:31
Date: Thu, 07 May 1992 01:31
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1670 bytes
In article <dfs.705083429@sarek> dfs@doe.carleton.ca (David F. Skoll) writes: >The problem is that these programs seem to be broken. I took a >standard-cell xnor, exported it with 'edifout', imported it with >'edifin', and the result was a very different cell. In particular, >'edifin' has problems with portImplementation constructs, always >converting the layer to 'wire' when the port is really on the 'dmet' >layer. > >Has anyone successfully used edifin and edifout? If so, how? I have encountered the same problems. The pins of a standard cell layout are not recognized once read into Cadence. There's problems with other terminals too, such as jumpers. Other layers such as PRBoundary are not recognized as well. I suspect those are bugs with edifin/out. I got around that by writing a SKILL program to fix the read in layouts, such as search for "wire" layers, and replace with "dmet". I could send you the program if you are interested. Carly Wong
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<1992May7.013138.1152@ee.ubc.ca>Path:
arc1-ca.pugleaf.net!sparky!uunet!usc!rpi!usenet.coe.montana.edu!news.u.washington.edu!uw-beaver!ubc-cs!fs1.ee.ubc.ca!carlywReferences:
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 109e85,cdd6c03aa35f3392,start X-Google-Attributes: gid109e85,public X-Google-Thread: f70d0,cdd6c03aa35f3392,start X-Google-Attributes: gidf70d0,public X-Google-ArrivalTime: 1992-05-06 18:31:38 PST Newsgroups: comp.lsi.cad,can.vlsi Path: arc1-ca.pugleaf.net!sparky!uunet!usc!rpi!usenet.coe.montana.edu!news.u.washington.edu!uw-beaver!ubc-cs!fs1.ee.ubc.ca!carlyw From: carlyw@ee.ubc.ca (Carly Wong) Subject: Re: Help wanted - Cadence Edge and EDIF Message-ID: <1992May7.013138.1152@ee.ubc.ca> Organization: University of BC, Electrical Engineering References: <dfs.705083429@sarek> Date: Thu, 7 May 1992 01:31:38 GMT Lines: 22