ECAD Software

Thread View: comp.lsi.cad

1 messages

[T] Back to Threads [V] Tree View [G] Group Articles

1 total messages Started by Colley M J Wed, 06 Apr 1994 11:42

#948

Author: Colley M J
Date: Wed, 06 Apr 1994 11:42

14 lines
1332 bytes

Now available via anonymous FTP from: ftp.essex.ac.uk

A Xilinx xnf -> verilog translator for generating postlayout verilog models
of placed and routed designs (XC3000 series only).

A Cadence Edge design kit for Xilinx XC3000 series devices. Allows schematic capture,
simulation, netlisting and postlayout simulation. Place and route must be done via
Xilinx tools.

These tools can be found in /pub/csc/ecad in source form.

Martin Colley

martin@essex.ac.uk

Thread Navigation

This is a paginated view of messages in the thread with full content displayed inline.

Messages are displayed in chronological order, with the original post highlighted in green.

Use pagination controls to navigate through all messages in large threads.

Back to All Threads