🚀 go-pugleaf

Bjorn B. Larsen (Bjorn.B.Larsen@delab.sintef.no) wrote:
: 
: Please forgive my, possibly, dumb question, but I really feel that
: IDDQ testing maybe is not the next step in production testing. (If we
: want something to replace testing for Stuck-At faults.)
: 
: [lines deleted]
:
: This leads me to 2 questions which I hope somebody out there in
: netland may cae to comment on:
: 
: 	1.	If a standard chip is specified to have Iddq = 150 mA,
: 		all tested chips (>> 100) show Iddq < 10 mA, and one
: 		chip shows Iddq = 125 mA. Would you accept the single
: 		125mA case? Is it likely to fail earlier than the ones
: 		with Iddq < 10 mA? What could be a reason for this
: 		atypical behaviour (though it is within spec)? (All
: 		chips are exposed to the same test.)
: 

If the spec is so far out of line with reality, then the spec should be
reconsidered. Simple data collection, as you indicate in this question,
indicates a single outlyer many sigma outside the normal distribution
(the unit with Iddq=125mA). Failure analysis of this device vs. one of 
the units from the normal distribution would, I'd expect, indicate a
problem with it of some sort (maybe not a functional problem, but maybe
leaky transistors or something like that). After functional verification 
(and maybe some non-standard tests like speed grading this part vs "known
good" parts, and measurement of Iddq at low and high temperatures) I'd
be tempted to pop the lid on the device, as well as a good unit, and look at 
both of them under an emission microscope. With a bit of luck that would be
somewhat likely to isolate the location(s) of the leakage. From there,
stripback and SEM to identify the cause (if possible, or if interesting).

: 	2.	What level would you require to measure on an Iddq test
: 		to claim that a chip has failed. (Spec says 150 mA)

I would take the distribution of data from several sample devices from
several lots over a period of time (depending on how many lots you run and
how stable your process is...), calculate the mean and std. deviation, then
set the limit at the mean + (some number, either 3 or 6)*std. deviation. I'd
then continue to monitor it. In a static CMOS circuit with no intended "ON"
transistors, Iddq should measure well under a milliamp, provided the devices
is in a known state.

: 
: Thank you for your time.

You're welcome. Hope that helps.

: 
: Bjorn
: --

Mike

-- 
----------------
Michael Kirschner
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[GEnie: M.KIRSCHNER1; well: obnoid]