Re: IDDQ Testing?

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Article #126

#126

From: Michael Kirschner
Date: Fri, 22 Jan 1993 16:00

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Terry Manley (manley@optilink.COM) wrote:
: In article <1993Jan19.231338.29821@newsgate.sps.mot.com> saari@chdasic.sps.mot.com writes:
: 
: >IDDQ testing is also necessary for the latent defects and catching faults in
: >redundant logic...
: 
: I'm unfamiliar with the term IDDQ testing. Would someone simply state the
: method of this test and it history?

Iddq is the the current drawn from Vdd while the device is in a static, or
"quiescent" state, hence "Iddq". It's only useful, to my knowledge, for
CMOS devices which are designed such that there are no intended resistive
paths from Vdd to ground while in some known state, e.g. immediately after
reset, with clock, if there is any, at a DC level.

: 
: Thanks,
: 
: dave
: manley@optilink.com

Mike

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Michael Kirschner
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From: obnoid@netcom.com (Michael Kirschner)
Subject: Re: IDDQ Testing?
Message-ID: <1993Jan22.160047.21804@netcom.com>
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Date: Fri, 22 Jan 1993 16:00:47 GMT
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