Article View: comp.lsi.testing
Article #129Re: IDDQ Testing?
From: Phil Pownall 1342476
Date: Mon, 25 Jan 1993 14:36
Date: Mon, 25 Jan 1993 14:36
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2882 bytes
Iddq is a current-measurement technique for detecting defects. Iddq, or quiescent Idd, is the (leakage) current which remains after a transition. In CMOS circuits, the quiescent current is very small (on the order of micro or nano amperes), and so Iddq is a particularly effective method for detecting defects such as gate-oxide shorts, which can raise the Iddq into the milliampere range. There is also widespread belief (with some evidence to back it up) that the kinds of defects that Iddq detects will often lead to infant mortality failures, and so Iddq could also be considered to be a reliability test. Iddq was first investigated and used (I Believe) by Ford Microelectronics in the early 80's. Other notable locations which have published results include Sandia Labs, Phillips Research, CMU and National Semiconductor. There are lots of papers on Iddq in the proceedings of the International Test Conference, for example. In essence, Iddq testing could be considered to be essentially the same as scan-based testing, except it uses the power & ground lines to observe the defect mechanism rather than scanning out a voltage value using the scan shift register; both techniques rely on having a high-coverage pattern to sensitise the defect. In addition, Iddq also requires that other sources of leakage current are controlled (e.g. dynamic memories, pullup resistors on input pads, etc) so that the Iddq value is as small as possible. Iddq values generally follow a normal distribution centred around a very small value, and so the test method basically involves deriving a margined test value similar to any other parametric test. Scan-based patterns have frequently been used for Iddq because they obtain high internal node coverage, and they are quite predictable in their timing behaviour. Many vendors of scan & design-for-test tools have the capability to generate a scan-based pattern for Iddq. The main difficulty with the test method has been the measurement speed. Since the values are so small, a certain amount of settling time has to be allowed. Some proponents have designed their own low-current measuring instruments, others have used the tester parametric measurement unit, and others have used the power supplies. Regards, Phil Pownall philp@bnr.CA
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Newsgroups: comp.lsi.testing Path: arc1-ca.pugleaf.net!sparky!uunet!cs.utexas.edu!torn!nott!bnrgate!bcrka451!bcrka449!philp From: philp@bcrka449.bnr.ca (Phil Pownall 1342476) Subject: Re: IDDQ Testing? Message-ID: <1993Jan25.143648.14303@bcrka451.bnr.ca> Sender: 5E00 Corkstown News Server Reply-To: philp@bcrka449.bnr.ca (Phil Pownall 1342476) Organization: Bell-Northern Research, Ottawa, Canada References: <13968@optilink.COM> <1jfmmhINNpc5@hpscit.sc.hp.com> <1993Jan19.231338.29821@newsgate.sps.mot.com> Date: Mon, 25 Jan 1993 14:36:48 GMT Lines: 41