🚀 go-pugleaf

            Bay Area Cadence User People (BACUP) Meeting
             Tuesday, December 2, 1997, 12-5:15 PM
                  Cadence Design Systems, Inc.
              2655 Seely Avenue, Bldg. 5, San Jose, CA


This user meeting is free and open to all Cadence and CCT product users. 
Please invite your colleagues and fellow users. If you would like to
receive future BACUP announcements, please send email to:
bacup_subscribe@gurutech.com. For more information about user group
activities, please contact Nora Reichel or visit the Cadence User Group
website: http://www.dacafe.com/USERSGROUPS/Cadence

SPACE IS LIMITED. Please RSVP by Wednesday, November 26th, 1997 to Nora
Reichel (nora@cadence.com), 408/944-7579, or Shankar Hemmady
(hemmady@gurutech.com). With your RSVP, please include your mailing address
and specify if you are attending lunch. SURPRISE GIFT to the first 35
RSVPs received. Must be present at the meeting to receive gift.


                     Tentative Meeting Agenda

12:00    Lunch and networking. Light lunch provided by Cadence.

1:00     Welcome and Introductions, Agenda Review and BACUP Business
         Shankar Hemmady, BACUP Chairperson

1:05     1997 User Conferences  Review (ICU & CCT) - Pats Shriver, Cadence
         1998 ICU Conference Update/Plans - Pats Shriver, Cadence

1:15     Performance Engineering Transition Plans - Steve Chidester, Cadence
         This presentation will outline the new product configurations and 
         describe the transitions that will affect you.

1:45     SPECCTRA Product Overview - Anthony Williams, Cadence          

         This presentation will tell you how SPECCTRA, the industry's leading 
         shape-based autorouter, can help you solve your tough design 
         challenges.

2:15     GUEST KEYNOTE: Deep Submicron Design Methodologies
         Jonah McLeod, Editor-in-Chief, Integrated System Design Magazine

3:15     Cadence Mixed-Signal Products Update

3:50     Refreshments Break/Raffle (HP Palm Top PC and Sun/Java Jacket)

4:05     Gaining the Competitive Edge for Complex System-On-Chip Design
         Mr. Misha Burich, Vice-President of Engineering, Alta Group Overview 
         of the importance of using system-level design methodologies for 
         successful risk and complexity management in system-on-chip designs.
     


Nora Reichel
Sr. User Group Relations Specialist
Ph 408/944-7579, Fx 408/570-3829
Email:  nora@cadence.com

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Shankar G. Hemmady                                             408-255-6300
Guru Technologies, Inc.                                    fax 408-257-7756
VLSI Design, Test & EDA Consulting                         www.gurutech.com
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  Office Address: 20370 Town Center Lane, Suite 245, Cupertino, CA 95014
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