Article View: comp.lsi.testing
Article #25Re: Benchmark Circuits for Digital circuit test pattern generation
From: Bjorn B. Larsen
Date: Fri, 21 Aug 1992 12:10
Date: Fri, 21 Aug 1992 12:10
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3425 bytes
In article <18341.2a92f106@levels.unisa.edu.au> 8809787l@levels.unisa.edu.au writes:
>In many papers in the field of fault diagnosis and Test generation for digital
>circuits I have seen benchmark circuits used to make comparison between the
>speed and effeciency of various test generation methods.
>I have commonly seen labels such as C880, C5315 or C7552 used to describe or
>mension these benchmark circuits. In many papers on this topic also I have seen
>the following reference to this circuits mensioned:
>(*) F. Brglez and H. Fujiwara, "A neutral netlist of ten combinational
>benchmark circuits and a target translator in FORTRAN," in Proc. IEEE Int.
>Symp. on Circuits and Systems, Kyoto, Japan, June 5-7, 1985
>[ ... ]
>I need to know the following:
>(1) What are these benchmark circuits ?
They are combinational circuits. I think they are parts of, or
complete, real designs. The number of Inputs and Outputs, and the
complexity of the circuits varies.
Usually referred to as ISCAS-85 circuits.
There is a similar set of sequential circuits presented on ISCAS-89, I
think.
>(2) Where can I get these from ?
I think MCNC - Microelectronics Center North Carolina - in the US is
the correct address. I do not have any e-mail or other.
It is an ASCII netlist, based on TEGAS TDL. Easy to transform to
whatever format you need.
They are free available, so if you know somebody with a copy, you may
get a compy from them.
(I may send you what we have, 8 of the 10 (?) circuits.)
>(3) What is the Brglez & Fujiwara reference ( I could not locate it ) ?
It is a tape, distributed to interested participants on the symposium.
(And others later.)
>(4) How can I use the above benchmark netlist to test a test generation method?
A - Get a copy of the netlist
B - Transform the netlist to the netlist_of_your_choise
C - Run your ATPG
D - Compare your results with other results. These you may find in
conference proceedings or journals.
>(5) Is there a updated version of this which has come out since 1989 ?
They vere issued in 1985, 1989 was the year of the sequential
circuits, if my memory serves me right.
What is there to update on a netlist? These are supposed to be
standard circuits which anybody may use to get comparable results from
ATPGs or fault simulators. I hope nobody has changed them.
Bj{\o}rn
--
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| | | Bjorn B. Larsen bjorn.b.larsen@delab.sintef.no
|__ |__ | SINTEF DELAB
| \| \| N-7034 TRONDHEIM tel: +47-7-592682 / 592600
|__/|__/|_ NORWAY fax: +47-7-591039 / 594302
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Newsgroups: comp.lsi.testing Path: arc1-ca.pugleaf.net!sparky!uunet!mcsun!sunic!ugle.unit.no!ugle.unit.no!Bjorn.B.Larsen From: Bjorn.B.Larsen@delab.sintef.no (Bjorn B. Larsen) Subject: Re: Benchmark Circuits for Digital circuit test pattern generation In-Reply-To: 8809787l@levels.unisa.edu.au's message of 19 Aug 92 15:40:29 GMT Message-ID: <BJORN.B.LARSEN.92Aug21121009@engels.delab.sintef.no> Sender: news@ugle.unit.no (NetNews Administrator) Reply-To: bjorn.b.larsen@delab.sintef.no Organization: delab References: <18341.2a92f106@levels.unisa.edu.au> Date: 21 Aug 92 12:10:09 Lines: 73