🚀 go-pugleaf

I'd like to ask the netters involved in IC testing, especially
educational institutions, if they have constructed/assembled digital
functional testers that would match the following specifications. We
are very interested in a low lost / low end solution for digital
functional testing in an educational environment.  If you have the best
solution, we would like to talk to you about licensing it for use in
Canadian Universities. 

Please e-mail to me. I will summarize to the net if there is sufficient 
interest.


Yoo Ho Cho

======================Specs==========================================

Specifications for a Low-End Digital Tester


1	# of pins ( I/O )		48/64 Splittable bi-directional
					I/O

2	standard DUT card		48 pin used for 68 pin PGA
					( to be customized )

3	maximum data rate		min. 1 MHz and maximum 5MHz

4	memory				16K per channel

5	per pin waveform formatting	6-8 clock phases,
					timing generator, common timing,
					resource selectable on per pin 
					basis

6	waveform formatting		delayed NRZ and NZ

7	hooks for mixed signal		sync out or trigger pulse

8	timing precision		edge resolution 2ns

9	timing accuracy			edge placement +- 5ns

10	dead time			=< 10% of period

11	minimum pulse width		=< 10% of period

12	voltage range			0-5 volts programmable per
					pin basis

13	slew rate			0.5V/ns

14	driver impedance		50 ohms

15	driver current sourcing		5mA ( four SLTTL )

16	driver current sinking		5mA

17	comparator			dual threshold

18	PMU				nice to have, not neccessary

19	dynamic Idq			Idq vs time, same resolution as
					timing generator

20	memory reload time		must be reloadable

21	voltage accuracy		
	 a. driver			+/- 50 mV
	 b. power supply		+/- 50 mV
	 c. compare threshold		+/- 50 mV

22	interface			Sun workstation prefered
					Other UNIX Workstations/IBM PC
					(IEEE 488 interface would be nice)