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Article #65Re: Boundary Scan JTAG 1149.1 Experience?
From: Alvin Jee
Date: Tue, 10 Nov 1992 22:24
Date: Tue, 10 Nov 1992 22:24
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In article <12867@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes: >As I understand it, consultants were hired to do the major part of the >IC design for the 10K - including the scan design. They subsequently >came out with a product for testing scan designs and tried to sell it - >unsuccessfully - under the banner "Gillytronics". Seems like something >was lacking in their methodology. > >Arnold Frisch >Tektronix Laboratories Actually, as I understand it :), the 10K was not designed by consultants; rather, the design was given to a company to implement using their scan and gate array technology. The company was called Integrated CMOS Systems, but is now called Vertex. Gillytron was the ATE vendor that they bought some equipment from. Vertex had their own scan stuff working before the 1149 standard was approved and have since modifed their stuff to become JTAG compliant (I think). Anyways, I believe that Vertex is still around as a subsidiary of Toshiba. Alvin Jee alvin@cse.ucsc.edu
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Path: arc1-ca.pugleaf.net!sparky!uunet!think.com!ames!agate!darkstar.UCSC.EDU!alvin From: alvin@cse.ucsc.edu (Alvin Jee) Newsgroups: comp.lsi.testing Subject: Re: Boundary Scan JTAG 1149.1 Experience? Date: 10 Nov 1992 22:24:39 GMT Organization: University of California, Santa Cruz (CE/CIS Boards) Lines: 22 Message-ID: <1dpcr7INNqtf@darkstar.UCSC.EDU> References: <12860@sail.LABS.TEK.COM> <BxH4w7.ts@scd.hp.com> <12867@sail.LABS.TEK.COM> NNTP-Posting-Host: arapaho.ucsc.edu