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Article #66Re: Boundary Scan JTAG 1149.1 Experience?
From: Stephen Vinoski
Date: Tue, 10 Nov 1992 22:45
Date: Tue, 10 Nov 1992 22:45
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3147 bytes
In article <12867@sail.LABS.TEK.COM> arnief@sail.LABS.TEK.COM (Arnie Frisch) writes: >>Do you realize that the DN10000 scan architecture was developed before >>1149.1? How can you accuse us of "departing from the standard" when >>the standard wasn't even around when we did this work? > >Do you realize that JTAG (the Joint Test Action Group) had been working >on this for about 8 years, and that they were well ahead of the DN10000 >architecture when they started writing the basis for the P1149.1 >standard? The DN10000 architecture work began in 1985, and we had a working system in 1987. This included power-up self tests that utilized pseudorandom scan test techniques, an offline scan test program that tested the system with automatically-generated scan patterns, and a remote debugger that allowed access to the system under test from any other workstation on the net. We never would have finished any of this if we had waited for 1149.1; the market window for the DN10k would have closed by then. What do you mean when you say that the 1149.1 folks were "well ahead" of us? Especially given the fact that we completed our work before they published the standard? Just because they were working on 1149.1 for a portion of the time that we were working on the DN10k doesn't mean that their work was anywhere near being ready to be put to use in a real system. Be practical, Arnie. >As I understand it, consultants were hired to do the major part of the >IC design for the 10K - including the scan design. They subsequently >came out with a product for testing scan designs and tried to sell it - >unsuccessfully - under the banner "Gillytronics". Seems like something >was lacking in their methodology. Sorry, Arnie. You're talking to a member of the DN10k development team, so please get your facts straight. We did our own ICs using gate arrays from Integrated CMOS Systems (ICS). The scan architecture was largely the brainchild of Bulent Dervisoglu. His many papers and articles contain a lot of good information related to scan architectures and scan testing. (Judging from the content of your postings, you should read them sometime.) Gillytronics was somehow related to ICS, but that is their only (weak) link to the DN10k work. Remember, Arnie, they set out to do chip testing with a specialized test system, and we were doing system testing using a built-in service processor. Very different beasties altogether. Why are you so bent out of shape about this, Arnie? Seems like you need to broaden your horizons a bit. -steve
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Newsgroups: comp.lsi.testing Path: arc1-ca.pugleaf.net!sparky!uunet!news.tek.com!psgrain!charnel!rat!usc!cs.utexas.edu!sun-barr!decwrl!sdd.hp.com!scd.hp.com!hpscdm!hpscdc!vinoski From: vinoski@ch.apollo.hp.com (Stephen Vinoski) Subject: Re: Boundary Scan JTAG 1149.1 Experience? Message-ID: <BxIv8L.Mrt@scd.hp.com> Sender: news@scd.hp.com (News Account) Organization: Hewlett-Packard Corporation, Chelmsford, MA References: <12860@sail.LABS.TEK.COM> <BxH4w7.ts@scd.hp.com> <12867@sail.LABS.TEK.COM> Date: Tue, 10 Nov 1992 22:45:57 GMT Lines: 48