🚀 go-pugleaf

Happy Monday All,

My task as a Diagnostic/Test Engineer is to create an embedded 
suite of tests to be run on power-up that will indicate a level 
of confidence in the functionallity of our realtime graphics 
training and simulation machine comprised mostly of 9U VME type
boards with lots of custom ASIC's.

I've performed this tasks a couple of times running hardware tests 
out of Eprom using a 680x0 processor.  The only limitation on past 
products was the amount of testability and observability designed 
into the product.  To improve test coverage for our next generation 
product we are designing boundary scan IEEE 1149.1 into all of the
ASIC's on our boards.  That's a total of 6,334 ASIC pins on one 
board alone!  I've already decided that it would be wise to break
the board up into separate scan chains based on functional blocks.
We'll probably use TI's scan chain contollers and linkers and a
Motorola 68HC16 BIT processor.

The problem is that we have no 1149.1 resident experience and it 
looks like I'm going to be it!  I've read everything I can get my 
hands on.  Right now I'm reading about TI's ASSET PC based tools 
that help you write and implement diagnostic boundary scan tests.  
Additionally TI's Scan Engine software converts the tests written 
for their ASSET product for use on any 16bit microprocessor as an 
embedded (POST/BIT) application.  The problem I have is justifying
spending ~$50K for these tools because most everyone around here who 
has heard anything about 1149.1 thinks that "writing software for a 
serial test bus should be a piece of cake"!  

Ya, Right!  Why would TI, HP, Teradyne... have entire development 
efforts underway if it was easy?  I have no experience in this so 
I can't defend my belief that this is going to be one huge pain in 
the butt!  I'd rather be helping the hardware engineers debug their 
hardware than my boundary scan software.  

Does anyone out there have any experience writing or spec'ing embedded 
or otherwise boundary scan tests or the use of any 1149.1 diagnostic 
tools or devices.  Was it "a piece of cake"?  What were the toughest 
technical hurdles.  Are there really a zillion ways to make an "off 
by one bit" error in the control software?  How many did you make?
I have a half million questions....

I also know that we could buy GenRad or HP ATE tools that will take 
care of this JTAG 1149.1 boundary scan testing automatically but we 
just don't have the product forecast to spend $700K just yet.

Can you help me with your experience, no matter how limited!?
Could you forward this message to someone you think might know?

Thanks All,

Ed Kearns
BBN Advanced Simulation Division
Bellevue, Washington
206-957-3271
ekearns@bbn.com

"It's Monday morning and the friggin' sun finally decides to come out!" 
- me, today.