JTAG 1149.1 && LSSD

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Article #8

From: John Hawkins P730
Date: Tue, 03 Nov 1992 20:46

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Hi all,

Just wondering...

Does JTAG care that the method I use to implement full-chip scan
on my ASIC is LSSD? I am using two-phase flip flops and generating 
the two clock phases (non-overlaping) on-board, so that only one 
test clock is necessary at the pin level.

How will this impact the JTAG module (1149.1 compliant) if at all?
Email & I'll summarize. Thanks.
Regards,

-- 
*John Hawkins --- Bell Northern Research,   Research Triangle Park,  NC  USA *
*MaBell: (919)9918579	email:jhawkins@bnr.ca	USnail:35 Davis Drive RTP,NC *
*Ham: KD4OKN                                                                 *
*------****-**------****-**------****-**------****-**------****-**------****-*

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Message-ID: <1992Nov3.204625.8510@brtph560.bnr.ca>

Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!bnr.co.uk!bmdhh243!bcars267!bnrgate!corpgate!brtph560!news

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Newsgroups: comp.lsi.testing
Path: arc1-ca.pugleaf.net!sparky!uunet!pipex!bnr.co.uk!bmdhh243!bcars267!bnrgate!corpgate!brtph560!news
From: hawkins@bnr.ca (John Hawkins P730)
Subject: JTAG 1149.1 && LSSD
Message-ID: <1992Nov3.204625.8510@brtph560.bnr.ca>
Followup-To: jhawkins@bnr.ca
Keywords: help
Sender: jhawkins@bnr.ca
Organization: Bell Northern Research, Research Triangle Park,NC
Distribution: usa
Date: Tue, 3 Nov 1992 20:46:25 GMT
Lines: 18