JTAG 1149.1 && LSSD

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3 total messages Started by John Hawkins P730 Tue, 03 Nov 1992 20:46

Author: John Hawkins P730
Date: Tue, 03 Nov 1992 20:46

18 lines
1157 bytes

Hi all,

Just wondering...

Does JTAG care that the method I use to implement full-chip scan
on my ASIC is LSSD? I am using two-phase flip flops and generating 
the two clock phases (non-overlaping) on-board, so that only one 
test clock is necessary at the pin level.

How will this impact the JTAG module (1149.1 compliant) if at all?
Email & I'll summarize. Thanks.
Regards,

-- 
*John Hawkins --- Bell Northern Research,   Research Triangle Park,  NC  USA *
*MaBell: (919)9918579	email:jhawkins@bnr.ca	USnail:35 Davis Drive RTP,NC *
*Ham: KD4OKN                                                                 *
*------****-**------****-**------****-**------****-**------****-**------****-*

Re: JTAG 1149.1 && LSSD

Author: Mourad B. Takla
Date: Wed, 04 Nov 1992 21:05

7 lines
696 bytes

Hi All,
	
	I am looking for the JTAG 1149.1 standard. Any information about
how to get those standards is appreciated. 

Thanks
Takla

Re: JTAG 1149.1 && LSSD

#63

Author: Edward Joseph Kearns
Date: Tue, 10 Nov 1992 01:30

24 lines
772 bytes

takla@r1w4.pub.utk.edu (Mourad B. Takla) writes:

>Hi All,
>	
>	I am looking for the JTAG 1149.1 standard. Any information about
>how to get those standards is appreciated. 

>Thanks
>Takla

Write to:

IEEE Service Center
P.O. Box 1331
445 Hoes Lane
Piscataway, N.J. 08855

or call:

1-800-678-4333

Ed Kearns
BBNASD
Bellevue,Washington

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