🚀 go-pugleaf

In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes:
> 
> I am currently involved in a design that is going to silicon. A design
> issue that is currently worrying me is the implementation of flag
> synchronizers that are reliable at high clock rates (around 25 Mhz). I
> can't really afford package pins (and their associated propagation
> delay) necessary to place these flops externally - they need to be on
> the chip.
> 
> I am interested in hearing about any experiences that any of you may
> have had concerning metastable effects in various synchronizer designs, 
> 

Here is a circuit design of my own that works very well in HCT, HC, LS,
and F logic families using the '74 D flip-flop.

Since the D input is tied high it cannot transition during the
mestastability (instability!) window which brackets the positive clock
transition.  This makes this design potentially metastable-immune.  I
say "potentially" because it depends on the "correct" internal design
of the D flip-flop.  So far, my use and testing shows exellent results.
I cannot claim to have exhaustively tested the circuit to the extent
that guarantees can be given for any application, but in my applications
it has worked well.

                                +
                                |
                                |
                                O  
                          ------------
                         |      P     | 
                  + -----|D          Q|-----
                         |            |
                         |            |
                clk -----|>           |
                         |            |
                         |           _|
                         |           Q|O------------ OUTPUT
                         |      C     |
                          ------------
                                O
                                |
                                |______________________________________
                                                                      |
                                                                      |
                                                                      |
                                +                                     |
                                |                                     |
                                |                                     |
                                O                                     |
                          -------------                               |
                         |      P      |                              |
                  + -----|D           Q|-----                         |
                         |             |                              |
                         |             |                              |
                clk -----|>            |                              |
                         |             |                              |
                         |            _|                              |
                         |            Q|O------------------------------
                         |      C      |
                          -------------
                                O
                                |
                                |
    INPUT -----------------------


I prefer my synchronizer circuit shown here over the traditional
multiple-stage shift-in (two or three stage shift-in) method.

The obvious limitation is that the input signal toggle rate must be
less than 1/2 the clock rate, and a symmetric clock period is assumed.

Steven M. Ward
ward@cfa.harvard.edu

   
                                |