🚀 go-pugleaf

I work on A/D converters, where metastability in the comparators, as a
result of comparators being "right on the edge", is a problem.  Tek's
oscilloscopes contain trigger circuits, which are essentially asynchronous
state machines, where metastability results in "trigger jitter".  In both
cases, the answer is the same:

   1)  Make the bistable feedback circuit damn fast
   2)  Give the circuit as much time as possible to "make up its mind"

Fancy biasing schemes don't often help much - they only change the 
conditions that cause metastability.  The best scheme is usually a 
digital pipeline, which passes on unresolved signals, allowing later
stages to make a decision.  The decision made under these conditions
is, of course, arbitrary, but nonetheless takes time to "create out of
nothing".  

The bistable circuit inside a fast TTL IC may have time constants
in the low hundreds of picoseconds, even if the part's gate delay is
many nanoseconds.  A MOS gate array flipflop is much slower, especially
if the flipflop is loaded, so even best case there will be more
metastability problems.  If using such a flipflop, you should make sure
the output is very lightly loaded, or use a cell with buffered outputs
that are not part of the feedback loop.

The metastability of the system will be on the order of exp[ -TIME/tau ]
where TIME is the minimum resolution time, and tau is the bistable
circuit's time constant.  Find tau by playing with SPICE.

Good Luck!

-- 
Keith Lofstrom   ...!tektronix!vice!keithl   keithl@vice.TEK.COM
MS 59-316, Tektronix, PO 500, Beaverton OR 97077  (503)-627-4052