🚀 go-pugleaf

In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes:
> I am currently involved in a design that is going to silicon. A design
> issue that is currently worrying me is the implementation of flag
> synchronizers that are reliable at high clock rates (around 25 Mhz). I
> can't really afford package pins (and their associated propagation
> delay) necessary to place these flops externally - they need to be on
> the chip.
> 
> Being burned by poor metastable characteristics in the past,  I am
> somewhat leary of flipflops as implemented in gate-arrays. There also
> seems to be a total lack of useful information from ASIC vendors on this
> subject. Apart from suggestions of multiple-ranking,  I have gotten
> nothing.
> 
> I am interested in hearing about any experiences that any of you may
> have had concerning metastable effects in various synchronizer designs, 
> as well as any suggestions on how to handle this phenomenon in the scope
> of the somewhat limited design options that the gate-array/standard-cell
> methodoligy offers. Also,  I would appreciate any good references. You
> can send me email if you'd like, or just post the stuff.
> 

You are absolutely right to be concerned and about the limits of most
design systems and libraries. One solution you might consider is the
Genesil silicon compiler from Silicon Compiler Systems. It includes
special functions for synchronizers and hand-shake elements specifically
to address these issues.




(fodder for the length checker)









phil