Re: metastability in ASIC synchronizer implementations

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Article #1041

#1041

From: Steve Pope
Date: Tue, 29 Mar 1988 17:30

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In article <18661@sci.UUCP> phil@sci.UUCP (Phil Kaufman) writes:
>In article <26@xenon.UUCP>, kerl@xenon.UUCP (Dan Kerl) writes:
>> I am currently involved in a design that is going to silicon. A design
>> issue that is currently worrying me is the implementation of flag
>> synchronizers that are reliable at high clock rates (around 25 Mhz). I
>
>You are absolutely right to be concerned and about the limits of most
>design systems and libraries. One solution you might consider is the
>Genesil silicon compiler from Silicon Compiler Systems. It includes
>special functions for synchronizers and hand-shake elements specifically
>to address these issues.

Phil, I'm sure SCI has great stuff in this area, but they're not
the only ASIC operation that has a synchronizer macro.  The real
questions are: how is the synchronizer specified, what were the
design principles, how is operation verified or simulated?  And
does it work at 25 MHz? (A 40 nsec synchronization interval
is pretty short for CMOS.)

steve

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Message-ID: <1930@pasteur.Berkeley.Edu>

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References: <26@xenon.UUCP> <18661@sci.UUCP>

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Path: arc1-ca.pugleaf.net!utzoo!mnetor!uunet!husc6!mailrus!ames!pasteur!zabriskie!spp
From: spp@zabriskie.uucp (Steve Pope)
Newsgroups: comp.lsi,sci.electronics
Subject: Re: metastability in ASIC synchronizer implementations
Message-ID: <1930@pasteur.Berkeley.Edu>
Date: 29 Mar 88 17:30:56 GMT
References: <26@xenon.UUCP> <18661@sci.UUCP>
Sender: news@pasteur.Berkeley.Edu
Reply-To: spp@zabriskie.UUCP (Steve Pope)
Organization: Postgres Research Group, UC Berkeley
Lines: 20
Keywords: synchronizer, flipflop, metastable, gate-array, standard cell

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