🚀 go-pugleaf

In article <41352@tut.cis.ohio-state.edu> Dik Lee <dlee@cis.ohio-state.edu> writes:
>I like to hear from people who have experience with wired-logic or
>know some references. I am interested in both nMOS and cMOS.

Putting pullups in parallel would render nMOS useless, unless there
were seperate cell-designs for each level of parallelism (i.e., design
with N cells in parallel, use versions of the N cells that have pullups
N-times the length of a standalone cell's pullup; now, explain to the
boss that the N-squared increase in pullup area and factor of max{N} cost
increase in cell-library maintenance is somehow involved in "savings"...)

Further, Wired-Or is anathema to CMOS.  The first time the pullup of
cell-A and the pulldown of cell-B simultaneously went "on", you'd be
working in a (most probably unbalanced) ratioed region, wherupon Vout
becomes (if you're lucky) about 2.5 volts.

				--Blair