🚀 go-pugleaf

In article <2462@buengc.BU.EDU> bph@buengc.bu.edu (Blair P. Houghton) writes:
>In article <41352@tut.cis.ohio-state.edu> Dik Lee <dlee@cis.ohio-state.edu> writes:
>>I like to hear from people who have experience with wired-logic or
>>know some references. I am interested in both nMOS and cMOS.
>
>Further, Wired-Or is anathema to CMOS.  The first time the pullup of
>cell-A and the pulldown of cell-B simultaneously went "on", you'd be
>working in a (most probably unbalanced) ratioed region, wherupon Vout
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>becomes (if you're lucky) about 2.5 volts.
>
>				--Blair


I think this is the idea in any sort of wired-OR application.  The general
idea is that you have a weak common pull-up (pseudo NMOS) that can easily
be over powered if any of the pull-downs go active.  Having pull-up and 
pull-downs of equal strength produces a power-hungry majority circuit at
best, not a wired-OR.

Wired-OR is only anathema to CMOS in that it dissipates static power, as
NMOS does, (and may or may not have a longer settling time) which the original
poster mentioned.  (There is a niggling change in noise immunity as well, but
I won't worry about that here, since it shouldn't be a problem as long as you
use fully restored signals on your inputs, don't have thousands of inputs, and
have a reasonably stable power supply.) If you have an application with a large
number of inputs to a gate, can afford the static power, have a desperate urge
not to use the area required for active pull-ups, and don't have any gating
signals available for a standard precharged solution, then wired-OR logic may
be the way to go, even in CMOS.  But you should know what you are doing
(ie. don't do this on your first student project) and it should be avoided if
there is a reasonable alternative.

--Charles
  flaig@apple.com