🚀 go-pugleaf

Hi, folks.

Is there anybody who designed a delay line(DL, continuous time, digital) 
using CMOS ?

Its specifications are as follows:

1. the output is delayed version of input.
2. it's desirable to have the symmetric delay
   (that is, rising propagation delay == falling propagation delay)
3. the delay must be controllable from "0.5ns" to "10ns"
   using only circuit parameter(let's say, using gate cap. or ratio...)
4. the total area of the DL must be minimal.
   (it can be included inside the usual Digital VLSI,
	in quantity of 10 or more)
....

I think somebody in the DRAM business might be using DL 
as a control signal for the RAS/CAS,
my application is totally different, though.

Any hints really will be appreciated.


- Ian Knight