🚀 go-pugleaf

In article <5855@m2c.M2C.ORG> chrisv@nuvlsi.coe.northeastern.edu (Chris Vagnini) writes:
  >I'm looking for a design for a dynamic ram sense amp and precharge
  >circuit.  The circuits I've found in textbooks are generally pretty
  >abstract or obviously wrong.  I've not been able to design a very good
  >one myself, either.
  >
  >Industry considers these designs, even old ones, extremely valuble,
  >but I have to assume that someone somewhere in academia has designed
  >and built a dynamic ram. I'd appreciate hearing about any public-domain
  >or publicly-distributable designs out there.  This is to be a part of a 
  >thesis project, a risc processor.


I'll let you in on a seldom-openly-stated fact: the circuit schematic
(topology and device sizing) of a DRAM sense amp and its precharge
circuitry is rather simple.  The hard work (and boy is there ever a
lot of hard work!) is in perfecting the polygon layout of these.
Criteria, starting with the most important, are

     (1)  Balanced capacitance.  Achieved ONLY through identical layout;
          it is not acceptable to assume that Y square microns of so-and-so
          has the same capacitance as Z square microns of thus-and-such.
          (what if the fab process wanders?  remember that DRAM design is
          an excercise in getting yield at the +/- 4 sigma extremes).

     (2)  Balanced capacitance when the layers are misaligned, when
          some of the layers are under-etched, over-exposed, etc.

     (3)  Balanced capacitance to control signals.  You want the effect of
          coupling from precharge clocks, equalization signals, samp strobes,
          etc. to be perfectly common-mode.  Even when masks misalign etc.

     (4)  Small area.  Sloppy design can easily lead to a DRAM chip which
          actually has less than 50% of its die area occupied by RAM cells.

     (5)  Reasonable drive-ability.  Remember that you are going to have
          an array of 512 or 1024 or 2048 of these puppies, driven from
          one end.  Distributed resistance (in the metal signal lines)
          and capacitance can ruin a cavalier design.

     (6)  Low parastic series resistance (e.g. nonminimum contact spacing
          to gate poly).  Make sure the samp is resistively balanced.


Lots of schematics for these are published; see the October issues of
the IEEE Journal of Solid State circuits for dozens of examples.

For a concrete example, the 1-Meg DRAM that I published (IEEE JSSC,
Oct. 1985, pp. 894-902) includes the sense amp and precharge circuit
schematic as Figure 4.  There are no other "hidden" or "secret"
transistors; what's in Fig. 4 is all that's on the 1-Megabit die.
The followig transistor sizes will suffice as a starting point:

     SAMP:         20/2        Precharges: 10/2
     Restore Amp:  20/2        Block Sel:   6/2

W and L are given in "Lambdas" ... though it burns my tongue and twists
my gut to publicly use that repugnant idea.
-- 
 -- Mark Johnson	
 	MIPS Computer Systems, 930 E. Arques M/S 2-02, Sunnyvale, CA 94086
	(408) 524-8308    mark@mips.com  {or ...!decwrl!mips!mark}