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Article #409zycad logic simulation strange behavior
From: Cindy Eisner
Date: Mon, 05 Oct 1992 08:15
Date: Mon, 05 Oct 1992 08:15
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i have the following strange behavior on a full chip simulation: some of
the ff's (which are modeled using the zycad primitive dffq) go to x (unknown)
in the middle of the clock and then recover before they are needed - i.e.,
the test runs fine, but you have x's all over the waves. i have not been
able to recreate this behavior on a small test case. so: before i go
plunging in to debug this - maybe someone has seen this before, or has some
ideas. what could cause this behavior from the dffq primitive. btw, the
prebar and clrbar inputs are constant at 1 throughout the simulation.
thanks,
cindy.
--
Cindy Eisner, Tel: 972-4-551551
CAD group, Fax: 972-4-551550
Zoran Microelectronics LTD, E-mail: cindy@Zoran.HellNet.Org
Advanced Technology Center
Haifa 31204, Israel Could be my employer doesn't agree.
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Path: arc1-ca.pugleaf.net!sparky!uunet!imp!ca41!cindy From: cindy@zoran.hellnet.org (Cindy Eisner) Newsgroups: comp.lsi Subject: zycad logic simulation strange behavior Keywords: zycad Message-ID: <175@ca41.zoran.hellnet.org> Date: 5 Oct 92 08:15:08 GMT Sender: news@ca41.zoran.hellnet.org Organization: Zoran Microelectronics LTD. Haifa, Israel. Lines: 19 Nntp-Posting-Host: ca45