Article View: comp.lsi
Article #410Re: Capacitance Estimation
From: Sandeep Srinivasan
Date: Thu, 05 Nov 1992 06:08
Date: Thu, 05 Nov 1992 06:08
16 lines
952 bytes
952 bytes
hi, to estimate approx equivalent diffusion/gate capitance knowing devices sizes ( i.e. W/L ) there is a nice paper called " Logical effort:Designing for Speed on the Back of an Envelope" by " Ivan E. Sutherland and Robert F. Sproull" published in Advanced Research in VLSI 1991 UC Santa Cruz.. This gives a good picture of how to estimate capacitance/delay of paths in mos cktc... with limited knowledge of process paramaters... sandeep
Technical Details
Message-ID:
<1992Nov5.060814.20859@dvorak.amd.com>Path:
arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!decwrl!sun-barr!news2me.EBay.Sun.COM!exodus.Eng.Sun.COM!sun!amdcad!dvorak.amd.com!sandeepReferences:
<1992Nov3.200344.9424@pasteur.Berkeley.EDU>Show Full Headers
Complete Article Headers
Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!decwrl!sun-barr!news2me.EBay.Sun.COM!exodus.Eng.Sun.COM!sun!amdcad!dvorak.amd.com!sandeep From: sandeep@amd.com (Sandeep Srinivasan) Newsgroups: comp.lsi,comp.lsi.cad Subject: Re: Capacitance Estimation Message-ID: <1992Nov5.060814.20859@dvorak.amd.com> Date: 5 Nov 92 06:08:14 GMT References: <1992Nov3.200344.9424@pasteur.Berkeley.EDU> Sender: usenet@dvorak.amd.com (Usenet News) Organization: /etc/organization Lines: 16