Multi-port RAMs

Article View: comp.lsi

Article #462

#462

From: Alexander The Great Sherstinsky
Date: Tue, 22 Jan 1991 00:57

17 lines
1473 bytes

Hello,

I am going to ask what might seem a stupid question, but here it goes anyway:

I am trying to build a new parallel computer as part of my thesis.  At my 
disposal are off-the-shelf components as well as the ability to build custom
chips (with MOSIS).  Here is the problem:  The architecture could really 
benefit from having a large 5-port-read, 5-port-write RAM, all ports being 
independent. Does such a beast exist?  Or if I am going to design a custom 
chip for it, how to do it without wasting too much silicon real estate?

Any response concerning this matter will be greatly appreciated.
--
+-------------------------------+------+---------------------------------------+
|Alexander The Great Sherstinsky|me    |shers@masala.lcs.mit.edu|To become as  |
|Alexander Semyon Sherstinsky   |myself|shers@masala.lcs.mit.edu|refined person|
|Alex Sherstinsky               |I     |shers@masala.lcs.mit.edu|as possible.  |

Technical Details

Message-ID: <1991Jan22.005718.23369@mintaka.lcs.mit.edu>

Path:

arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!think.com!mintaka!daemon

Show Full Headers

Complete Article Headers

Path: arc1-ca.pugleaf.net!utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!think.com!mintaka!daemon
From: shers@masala.lcs.mit.edu (Alexander The Great                                                                 Sherstinsky)
Newsgroups: comp.lsi,sci.electronics
Subject: Multi-port RAMs
Message-ID: <1991Jan22.005718.23369@mintaka.lcs.mit.edu>
Date: 22 Jan 91 00:57:18 GMT
Sender: daemon@mintaka.lcs.mit.edu (Lucifer Maleficius)
Organization: MIT Laboratory for Computer Science
Lines: 17