🚀 go-pugleaf

In article <1991Jan22.005718.23369@mintaka.lcs.mit.edu> shers@masala.lcs.mit.edu (Alexander The Great                                                                 Sherstinsky) writes:

   chips (with MOSIS).  Here is the problem:  The architecture could really 
   benefit from having a large 5-port-read, 5-port-write RAM, all ports being 

Consider some alternatives : a Video RAM has one standard read/write port
and one serial read only port. Many vendors make multiport FIFO's;
check the non-mainline companies like Integrated Device Technologies. 
Pick up a copy of EE Times or Electronic Design News for more 
company names. There may be a few vendors making true multiport
RAM's; but I'd be surprised if they made 5 port versions. Another 
alternative is to use standard fast SRAM's and use external glue logic
to time-multiplex the ports (either on-demand, or fixed time 
window basis). 

Even if you made a chip out of it, you'd not get much memory out of it. 
For something like MOSIS' process, you'd be lucky to get a few K bytes
worth. Take a look at mask photographs of present day fast CMOS 
processors (Intel, Digital, AT&T, IBM, others; look at the Proc of
Custom Integrated Circuits Conference). On a large sized die with 
1 u or less processes, a 8Kbyte cache could take up half the area. 
MOSIS' process is probably nowhere as good. 

Best suggestion : use off the shelf SRAM's, that gets you enough Kbytes,
and use glue, PLD's or mosis ASIC to convert it into 5 port. 

Good luck, 

/ Jon Sreekanth

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