🚀 go-pugleaf

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> Given the following architecture body.
> D and E are converted to correct values, but F gives a 0.
> Any ideas why this doesn't work (especially since it works elsewhere)?

> architecure adder of adder is
>  signal d,e,f : integer;
>  begin
>   process (add_enable, add_in1, add_in2)
>     if (add_enable, = '1') then
>       d <= bin_int2(add_in1); -- convert 32-bit bit array to integer 
>       e <= bin_int3(add_in2); -- convert 40-bit bit array to integer 
>       f <= (d + e); -- add the integers together
>     end if;
>   end process;
> end adder;
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The problem here, is that f takes the present values of d and e (which
are either 0 or the left value of the integer type). The updated values of
d and e will be present on the next delta cycle. One possibility
is to add d and e to the sensititvity list of the process. You will
get the correct value on f some delta cycles later.



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