🚀 go-pugleaf

             WORKSHOP ON HIERARCHICAL TEST GENERATION
                        August 8-11, 1993
                    Blacksburg, Virginia  USA

Preliminary Call for Participation

Scope.  Complex VLSI systems present significant problems for test
generation.  Gate level fault models yield high quality tests, but their
application to circuits with hundreds of thousands of gates is
prohibitively expensive.  Better approaches to test generation for these
systems is a necessity.  With hardware description languages such as
VHDL, designs can be described in either a top down or bottom up
fashion through varying levels of abstraction.  However, there is a
corresponding need for an accompanying set of test generation
techniques that can work throughout the abstraction hierarchy.
Designers at different points in the design process need to generate
tests to validate their design models.  In addition, if testability is
considered early in the design process, test generation at all
subsequent design phases would be easier.  If hierarchical design
techniques are to be truly effective, corresponding test generation
techniques must be developed.

The first Workshop on Hierarchical Test Generation will bring
together researchers from the hardware description language, test, and
related communities to discuss these issues in a focused and
interactive forum.  Areas of interest include behavior-assisted gate-
level and switch-level test generation, test construction from sub-
component tests, and test generation from behavioral models.  The
workshop will assess the current state of hierarchical test generation
and establish research directions and goals for further development of
test generation techniques that can be applied to large and complex
circuits.  A concrete, immediate result of the workshop will be the
creation of a hierarchical test generation model suite that researchers
can use to evaluate and compare hierarchical test generation
techniques.  Plans for a second workshop, to be held in Germany in
August 1994, are already underway.

Workshop Location.  The first workshop will be held on the campus
of Virginia Polytechnic Institute and State University.  Virginia Tech
is in Blacksburg, Virginia, which is located in the scenic Blue Ridge
Mountains.  Air transportation is provided by the Roanoke, Virginia
airport.

Participation.  To maintain the focused format of the workshop,
participation will be limited.  If you would like to participate, please
complete and submit the application below.  If you would like to speak
at the workshop, also submit a one-page abstract of your presentation.
The application and abstract should be submitted to the appropriate
program chair listed below.  Electronic mail submissions are encouraged.

Sponsors.  Sponsorship is currently pending approval.

General Chair
James R. Armstrong
Electrical Engineering
Virginia Tech
Blacksburg, VA  24061  USA
telephone: (703) 231-4723
fax: (703) 231-3362
jra@vtvm1.cc.vt.edu

Program Chair
F. Gail Gray
Electrical Engineering
Virginia Tech
Blacksburg, VA  24061  USA
telephone: (703) 231-7059
fax: (703) 231-3362
fggray@vtvm1.cc.vt.edu

Program Co-Chair (Europe)
Walter Geisselhardt
Universitaet Duisburg
Fachbereich 9 Datenverarbeitung
Bismarckstr. 81
W-4100 Duisburg 1
Germany
telephone: 0203-379-2729
gd@du9ds3.uni-duisburg.de

Program Co-Chair (Asia)
Kozo Kinoshita
Osaka University
Suite 565, 2-1 Yamadaoka
Japan
telephone: 06-877-5111
kozo@ap.osaka-u.ac.jp

Important Dates:
    Applications due:  April 5, 1993
    Notification:      May 15, 1993
    Overheads:         July 26, 1993

--------------------------------------------------------------------

WORKSHOP ON HIERARCHICAL TEST GENERATION
AUGUST 8-11, 1992
BLACKSBURG, VIRGINIA  USA

PARTICIPATION APPLICATION

Name:

Affiliation:

Mailing Address:

Telephone:

Fax:

Electronic mail:

Briefly summarize your background and interest in hierarchical
test generation:

I would like to make a presentation at the workshop (yes or no):

Title of presentation:

PROSPECTIVE PRESENTERS SHOULD INCLUDE A ONE-PAGE ABSTRACT WITH
THEIR APPLICATION.

Submit application and abstract to the appropriate program chair
listed above by April 5, 1993.

-- 
|  |   / Dr. Holger Veit         | INTERNET: veit@du9ds3.fb9dv.uni-duisburg.de
|__|  /  University of Duisburg  | "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
|  | /   Dept. of Electr. Eng.   |   Sorry, the above really good fortune has
|  |/    Inst. f. Dataprocessing |      been CENSORED because of obscenity"