yield estimation in digital CMOS VLSI

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1 total messages Started by Brad Carlson Wed, 23 Dec 1992 19:53

#608

Author: Brad Carlson
Date: Wed, 23 Dec 1992 19:53

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Please reply to bcarlson@sbee.sunysb.edu

Can anybody tell me if a model exists for the distribution of the delay of a
digital CMOS VLSI circuit as a function of process parameter variation?
That is, given the nominal delay of a circuit, I want to estimate
the yield for a given operating frequency.
References to articles describing such a model are sufficient.

Thanks in advance,
Brad Carlson
SUNY Stony Brook

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