Re: Dual Celeron's and SMP Performance Problems

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#508

From: Rowan Hughes
Date: Wed, 26 May 1999 00:00

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In article <7iette$6ge$1@nnrp03.primenet.com>, Rod Roark wrote:
>I must be dense.  After reading this a couple of times I still don't
>understand: how can two Celerons be worse than one when each has its 
>own cache?  I don't see how an interrupt serviced by one would cause 

Well i've certainly had this experience on dual/SMP machines,
although not on X86/linux.

-- 
=======================================================
Dr Rowan Hughes                  hughesr@dnr.qld.gov.au
Qld Dept Natural Resources          Forestry Bldg, 4.06    
CIS group, Indooroopilly. W:07-38969705   H:07-38768083

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From: hughesr@nrpc.dnr.qld.gov.au (Rowan Hughes)
Subject: Re: Dual Celeron's and SMP Performance Problems
Date: 1999/05/26
Message-ID: <slrn7kmo5i.143.hughesr@nrpc.dnr.qld.gov.au>
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