🚀 go-pugleaf

On Mon, 17 Jun 2002 14:31:46 GMT, redelm@ev1.net.invalid (Robert
Redelmeier) wrote:

>In comp.sys.ibm.pc.hardware.chips George Macdonald <fammacd=!SPAM^nothanks@garden.net> wrote:
>:  On Sun, 16 Jun 2002 09:30:49 GMT, "Robert Myers" <rmyers1400@attbi.com>
>:  wrote:
>: >Without SSE2, which requires that loops be vectorized, a 1.7GHz P2 is a very
>: >weak foating point performer, as many have noted, and as you have confirmed
>: >for yourself.  If I take naive code compiled with icc, my overclocked
>: >Celeron running at 1.5MHz will beat a 1.7GHz P4 every time.
>:  
>:  Are you sure about this?  I thought the idea with P4's SSE2 was that for
>:  scalar calcs you have addressable registers (no stack) and therefore no
>:  need of the FXCH instructions for stack swaps and it runs faster than the
>:  old x87 FPU.  I've no experience yet but that's how I read things.
>
>Saving FXCH hardly matters.  The big difference is that SSE2 can
>do two double precision flops in parallel once the data has been
>vectorized.  IIRC, an FPU or SSE multiply takes 4 clocks and can
>be pipeline started every two clocks.  But the SSE will deliver
>two results in the halves of the 128bit XMM register, while the
>FPU will only deliver one 80bit result.

There are cases though where even matrix code is not amenable to
vectorization - sparse vectors and zero tolerance checking issues.  This
gets very messy with the x87 stack FPU and FXCH.

>SSE is a big advantage for vectorizable floating point calcs and
>is essential to match or beat AMD whose K7 architecture allows
>a great deal more multiple-issue parallel instruction processing.

It had been my impression that even with scalar code and using the SSE2
directly addressable registers, the P4 FPU could get as good or better
performance clock for clock as a PIII with code optimized for the x87 using
FXCH.

Rgds, George Macdonald

"Just because they're paranoid doesn't mean you're not psychotic" - Who, me??