Article View: comp.os.linux.hardware
Article #932Re: Mixing PIII processors with differing cache sizes
From: GrahamBanks
Date: Wed, 01 Jan 2003 13:02
Date: Wed, 01 Jan 2003 13:02
52 lines
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3639 bytes
"Jeremy" <jjs@yourwindowspartition.owc.net> wrote in message news:wcqQ9.28872$A%3.377753@ord-read.news.verio.net... > GrahamBanks wrote: > > > Intel's Processor Specification Update says: > > > > While there are no known issues associated with the mixing of processors > > with differing cache sizes in a dual processor > > system, and Intel has done nothing to specifically prevent such system > > configurations from operating, Intel does not support > > such configurations since there may be uncharacterized errata that exist. > > In dual processor systems, all processors must be of > > the same cache size. > > > > Is anyone aware of any issues with mixing processors with differing cache > > sizes? Has anyone successfully done it? > > > > -- > > Graham > > > The cache available on each processor will be equal to the amount of the > smaller cached proc. > > I think this statement was regarding Xeons...in which case you would be > wasting alot of money for that unused cache. With non-Xeon P3s, > different cache sizes can mean quite different procs with diff FSB speeds. > For example, you definately don't want to mix 100MHz FSB and 133MHz FSB > slot1s (which are 512k and 256k cache respectively). > > Really you should try to get identical steppings for SMP (look for someone > selling a matched pair) to ensure they will play nicely together. Or at > least check Intel's charts to ensure two different steppings are > compatible. > > Jeremy > __________________________________________________________________ > Please remove your windows partition when replying by email Sorry, I could have been more specific in my question. I have a server with 2 Xeon PIIIs already in and there were 2 more Xeons available to buy. These have the same stepping as the ones I already have, but a different (bigger) cache size. I was refered to Intel's Processor Specification Update by an earlier post, but this seemed non-comittal on the question of differing cache sizes, so I asked the question. I've bought the two extra processors now, and I'll be happy if they work as if they are two more of what I already have. Thanks for your reply.
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 1113fa,7c3fc51986e3bc17 X-Google-Attributes: gid1113fa,public X-Google-Thread: fdc9c,7c3fc51986e3bc17 X-Google-Attributes: gidfdc9c,public X-Google-Thread: 11196f,7c3fc51986e3bc17 X-Google-Attributes: gid11196f,public X-Google-Thread: 102b32,7c3fc51986e3bc17 X-Google-Attributes: gid102b32,public X-Google-ArrivalTime: 2003-01-01 05:03:45 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!sn-xit-02!sn-xit-06!sn-xit-08!supernews.com!news.tele.dk!news.tele.dk!small.news.tele.dk!newsfeed.icl.net!newsfeed.fjserv.net!diablo.theplanet.net!news.theplanet.net!not-for-mail From: "GrahamBanks" <gb@grahambanks.freeserve.co.uk> Newsgroups: comp.os.linux.hardware,comp.sys.ibm.pc.hardware.systems,intel.microprocessors.pentium_iii,redhat.hardware.arch.intel Subject: Re: Mixing PIII processors with differing cache sizes Date: Wed, 1 Jan 2003 13:02:32 -0000 Lines: 56 Message-ID: <auuou6$g97$1@news5.svr.pol.co.uk> References: <ausrm8$qji$1@newsg2.svr.pol.co.uk> <wcqQ9.28872$A%3.377753@ord-read.news.verio.net> NNTP-Posting-Host: 217.135.254.84 X-Trace: news5.svr.pol.co.uk 1041426182 16679 217.135.254.84 (1 Jan 2003 13:03:02 GMT) NNTP-Posting-Date: 1 Jan 2003 13:03:02 GMT X-Complaints-To: abuse@theplanet.net X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 5.00.2919.6700 X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700