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Article #933Re: Mixing PIII processors with differing cache sizes
From: Neo
Date: Thu, 02 Jan 2003 03:20
Date: Thu, 02 Jan 2003 03:20
27 lines
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3004 bytes
> > The cache available on each processor will be equal to the amount of the > > smaller cached proc. > > > > I think this statement was regarding Xeons...in which case you would be > > wasting alot of money for that unused cache. With non-Xeon P3s, > > different cache sizes can mean quite different procs with diff FSB speeds. > > For example, you definately don't want to mix 100MHz FSB and 133MHz FSB > > slot1s (which are 512k and 256k cache respectively). Actually, the processor will use what it has and running with mixed cache sizes is generally no problem. Software has no access to change the size of the cache (only to enable or disable). Part of the non-commital attitude is due to the unknowns of what software might do. This difference is a violation of SMP assumptions and could result in unpredictable behavior. If a piece of executed code is large or accesses a large amount of data (i.e. it runs better in a large cache processor than a small cache processor) and tries to do some routine timing, the results will be unpredictable as it will depend if the code is assigned to a large cache processor or a small cache processor. Being that most software does not do this, most things should run just fine. If you did have software that did exhibit a problem, you probably could set the application processor affinity and workaround it (as long as it wasn't the OS that caused the problem). Neo
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: 102b32,7c3fc51986e3bc17 X-Google-Attributes: gid102b32,public X-Google-Thread: 11196f,7c3fc51986e3bc17 X-Google-Attributes: gid11196f,public X-Google-Thread: 1113fa,7c3fc51986e3bc17 X-Google-Attributes: gid1113fa,public X-Google-Thread: fdc9c,7c3fc51986e3bc17 X-Google-Attributes: gidfdc9c,public X-Google-ArrivalTime: 2003-01-01 19:21:02 PST Path: arc1-ca.pugleaf.net!archiver1.google.com!news1.google.com!sn-xit-02!sn-xit-03!sn-xit-06!sn-xit-09!supernews.com!nntp.cs.ubc.ca!logbridge.uoregon.edu!arclight.uoregon.edu!wn14feed!wn12feed!worldnet.att.net!204.127.198.204!attbi_feed4!attbi.com!rwcrnsc52.ops.asp.att.net.POSTED!not-for-mail From: "Neo" <intel@attbi.com> Newsgroups: comp.os.linux.hardware,comp.sys.ibm.pc.hardware.systems,intel.microprocessors.pentium_iii,redhat.hardware.arch.intel References: <ausrm8$qji$1@newsg2.svr.pol.co.uk> <wcqQ9.28872$A%3.377753@ord-read.news.verio.net> <auuou6$g97$1@news5.svr.pol.co.uk> Subject: Re: Mixing PIII processors with differing cache sizes Lines: 29 Organization: Vertically oriented X-Priority: 3 X-MSMail-Priority: Normal X-Newsreader: Microsoft Outlook Express 6.00.2800.1106 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2800.1106 Message-ID: <aeOQ9.527512$%m4.149815@rwcrnsc52.ops.asp.att.net> NNTP-Posting-Host: 12.229.9.99 X-Complaints-To: abuse@attbi.com X-Trace: rwcrnsc52.ops.asp.att.net 1041477638 12.229.9.99 (Thu, 02 Jan 2003 03:20:38 GMT) NNTP-Posting-Date: Thu, 02 Jan 2003 03:20:38 GMT Date: Thu, 02 Jan 2003 03:20:38 GMT