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Article #934Does full-speed 256 L2 cache reduce SMP efficiency?
From: Steve Snyder
Date: Tue, 15 Feb 2000 00:00
Date: Tue, 15 Feb 2000 00:00
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1139 bytes
I have read that a full-speed 256KB L2 cache reduces SMP efficiency relative to a half-speed 512KB cache. For example, a P3/600e vs. a P3/600. Is this true? Is there greater benefit in SMP to a larger L2 cache, even if it is half as fast? Thank you. ***** Steve Snyder *****
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X-Google-Language: ENGLISH,ASCII-7-bit X-Google-Thread: fdc9c,259764916411d84e,start X-Google-Attributes: gidfdc9c,public X-Google-Thread: 102b32,259764916411d84e,start X-Google-Attributes: gid102b32,public From: "Steve Snyder" <swsnyder@home.com> Subject: Does full-speed 256 L2 cache reduce SMP efficiency? Date: 2000/02/15 Message-ID: <fjfalqreubzrpbz.fpz8zv0.pminews@news.nblvil1.in.home.com> X-Deja-AN: 586150200 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii" X-Complaints-To: abuse@home.net X-Trace: news1.rdc1.il.home.com 950627656 24.4.162.173 (Tue, 15 Feb 2000 07:14:16 PST) Organization: @Home Network MIME-Version: 1.0 Reply-To: "Steve Snyder" <swsnyder@home.com> NNTP-Posting-Date: Tue, 15 Feb 2000 07:14:16 PST Newsgroups: comp.os.linux.hardware,intel.microprocessors.pentium_iii