🚀 go-pugleaf

Dear friend,
thanks for your reply ...

> With my card, each DWORD takes 30 ns to be transfered, but between
> each group of 8 dwords, i have a period of 660 ns (22 cycles) without
> any activity.
>
> I have not this period of inactivity on motherboard (Pentium) with
> 82439TX based chipsed.
>
> > You can see the delays do NOT happen within the PCI transfer. The
> > delays happen AMONG transfers.
>
> Exactly..
>
> > The big question: Why???, what on the hell are doing the CPU or the
> > bridge during these time intervals?

OK ... the question is here: what happens during these time intervals?

Let me try an hypothesis. If the chipset is in charge to manage the PCI,
AGP and physical memory buses, then, may be, it requires time slots for
some housekeeping tasks. I say "housekeeping tasks" because these
inactivity times are always present. May be, it is not able to manage
simultaneosuly some housekeeping tasks and memory transfer orders.

For a while let us admit the hypothesis. What housekeeping tasks can be
there? My hardware knowledge is short, therefore I am going to expose me
to say silly things. I have heard dynamic memories need permanent and
continous accesses in order to maintain data. Is the chipset in charge?
Could it be the housekeeping task? Is this hypothesis fitting with your
82439TX experience?

Well ... as I told, next days I am going to try a VIA MVP3 chipset.



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