🚀 go-pugleaf

In article <4lh2u1$10rg@news-s01.ny.us.ibm.net>,
boisjol@ibm.net (Yves Boisjoly) says:

>	10 nano seconds !!!

>Since we know that a Pentium 100Mhz actualy reach that speed internally, and 
>in my case, on my mother board, the clock of the PCI and data bus is actualy 
>running at the speed of 66Mhz, how can a Pentium 100 Mhz (66Mhz external) can
>access those 60-70 nano seconds chips, at 0 WAIT STATE?

Simple.

There's two caches involved- one L1 cache *inside* the P5 processor, which
is running at the *internal* (this is important, later) speed of 100MHz, and
the static-RAM (SRAM) L2 cache, which is made up of very fast memory that's
got a speed of 15ns or faster. Also as you noted, P5 chips are clock-doubled
(if not clock-tripled), so you must increase your memory cycle times by at
least twice, as the external bus is running slower than what's on the chip.

Also, it's a rare event that a chipset will actually deliver "0" WS even if
the config options specify this- there's built-in, and required memory cycle
delays, as well.

	-Kenny

-- 
Kenneth R. Crudup, Unix & OS/2 Software Consultant, Scott County Consulting
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