🚀 go-pugleaf

In <4lh2u1$10rg@news-s01.ny.us.ibm.net>, boisjol@ibm.net  (Yves Boisjoly) writes:
>In <4l9eei$gil@news.aros.net>, John Brush@aros.net writes:
>>
>>I don't know who wrote this statement, and it really doesn't matter. However,
>>I am getting way sick of people who do not know have a clue 
>>making assumptions and giving the impression that they know what
>>they are talking about.
>>
>>Anyone who tells you that you can't mix speeds (meaning a 60ns in place of
>>a 70ns) is a bigger liar than the person who fits the above scenario. If your
>>motherboard and bios supports 70ns RAM, you can put 10ns Ram in those 
>>slots and the system won't give a rat's ass! If you put a SLOWER device in,
>>then you have a potential problem.
>>
>>Now for the corny line. I design embedded controllers and computer systems
>>and I know what I am talking about. Challenge me, flame me, I don't care.
>>I do know what I a talking about in this area. Can't we all just get along?
>>
>>Thank you.
>>
>>Regards,
>>
>>John
>
>Hi John,
>
>I am so happy. May be you can respond this old old old question that I have in my 
>mind since about 5 years...
>
>If we take a Pentium 100Mhz, and try to found it speed in nano seconds, am I right 
>if a use this formula:
>
>	frequency =1 / period
>
>so,
>
>	period = 1 / frequency
>
>means
>
>	period = 1 / 100 Mhz (100 000 000 hertz)
>
>equal
>
>	0.000 000 010 seconds
>
>means
>
>	10 nano seconds !!!
>
>Since we know that a Pentium 100Mhz actualy reach that speed internally, and 
>in my case, on my mother board, the clock of the PCI and data bus is actualy 
>running at the speed of 66Mhz, how can a Pentium 100 Mhz (66Mhz external) can
>access those 60-70 nano seconds chips, at 0 WAIT STATE ! ! ? ? ! !

Simply, it can't. 

As you point out, the external interface to the chip is 66 mhz, so any time
there is a L1 cache miss, and an off chip access occurs, there will be a wait
inserted.  If the L2 (on board) cache has doesn't have it, there are more
wait states inserted.  And there is a wait state while all these caches refill.

And if the memory has been paged out to disk, there are even more delays 
added.

The trick is with the memory caches, its possible to get very high hit ratios
on them, so that MOST of the code is running with few wait states, and on
the average things work out. 

                                                           -john