🚀 go-pugleaf

in article <961@manta.NOSC.MIL>, dwi@manta.NOSC.MIL (Steve Stamper) says:

> Will the A2630 board allow faster DRAMS on board like the A2620?

After a fashion.  The timing is adjustable, but requires a change to a
PAL or a delay line.  I'll probably work out some of the more interesting
configurations when I have a few free seconds.	Mabye next March...

> Seems at 25Mhz 100ns would mean a lot of wait states.

Two asynchronous cycle wait states.

> If faster DRAMS are used how fast should they be? 90 ns or 80 ns?

With the proper setup, it's possible to go a clock faster with good
80ns DRAM, though I'm not sure all 80ns parts are fast enough (you're
cutting 40ns off the entire cycle time, not just 20ns off the row
address access time).

> I presume one would have to remove the 2M of DRAM installed
> by the factory to put in faster RAM on the system.

Well, yes, but...

> I am planning to get one as soon as I can and would like
> to outfit it with 4M of the fastest DRAMS I can.

Before hacking my A2630 to bits, I'd wait a little and see who makes
daughterboards for them.  The daughterboard memory isn't DMAable, but
it could be run 0 wait states, and it can even support a tack-on
cache instead of additional memory.  Commodore has no current plans
to build an add-on memory board, but we did release the specs and
a couple of 3rd parties seem interested.  The memory bank size 
and free space on such a daughterboard would lend itself well to
a fast nybble mode memory design or even faster interleaved SCRAM
design.

> -Roger
-- 
Dave Haynie Commodore-Amiga (Systems Engineering) "The Crew That Never Rests"
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