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In article <1138@water.waterloo.edu> ljdickey@water.waterloo.edu (Lee Dickey) writes:
>In article <607@sbcs.UUCP> root@sbcs.UUCP (Root) writes:
>>> >      One article I have seen quotes the performance of the slower T414
>>> >      processor (20 mhz) as 10 MIPS !
>>
>>	RISC mips, unfortunately. 
>
>You seem to imply that RISC mips are not quite as good as some other kind
>of MIPS.  Are RISC mips slower somehow?  Are more instructions needed to
>produce the same results?   Explain, please.
>
>-- 
> L. J. Dickey, Faculty of Mathematics, University of Waterloo. 
> ljdickey@watmath.UUCP		UUCP: ...!uunet!watmath!ljdickey
> ljdickey%water@waterloo.edu	ljdickey@watdcs.BITNET		
> ljdickey%water%waterloo.csnet@csnet-relay.ARPA

I do not dare to compare ALL Risc type processors to the 68*** family of
processors. I can however comment a bit on the T-series from Inmos.

Inmos has three general purpose transputers and a couple of dedicated transputers. These are: the T212 the T414 and the T800 (the latter is available in test
quantities only right now).
The T212 is a 16 bit transputer with a 16 bit data AND address bus, thus
being capable of addressing at most 64 KiloByte.
The T414 is a 32 bit transputer with 32 data and address bus.
The 800 is also a 32 bit transputer but in addition it has a on chip 64 bit
IEEE floating point unit.

The T414 is comparable to the 68000 or 68010, and the T800 is comparable
to the set 68020/68881.

All transputers have a memory interface, 2 KiloByte onchip memory (4Kb for
the T800) and 4 serial interfaces. The serial interfaces are electrically
asynchronous serial links on which a synchonous protocol is implemented in
the micro code level. The serial links run at 20 MegaBits per second.

The T800 is clocked at 20 MHz (and planned for next year? at 30 Mhz). The
floating point unit operates at a speed of 1.5 MegaFlops. The main processor
operates at a speed of 10 MIPS.

Using the serial links (just two wires) it is very easy to built a network of
transputers (well, a multi processor system). Data transfer primitives are
implemented for them, also in micro code.

The transputers are multi tasking processors. Multitasking is also supported
by the hardware/micro code, resulting in a context switch that takes no more
than 2 to 4 MicroSeconds.

For processes running concurrently on the same processor the same data
transfer primitives as those used for the serial links can be used.

The transputers do not have on chip registers as the 68*** processors have.
In stead they have a so called evaluation stack that works very similar to
the register stack in a Hewlett Packard calculator. The instructions of the
transputers are all the same length, making decoding easier and faster. Also
there are a lot less instructions than in the 68***. This makes that possibly
more instructions are needed on a transputer than on a 68***. 

The following table is published in several Inmos publications on the
transputer performance (note that this is not a MIPS/Flops rating, but a more
or less 'real-life' rating):

	processor		clock		Whetstones/second

	Intel 80286/80287	8 MHz		300 000
	Inmos T414		20 Mhz		663 000
	NS 32332/32081		15 Mhz		728 000
	MC 68020/68881		16/12 Mhz	755 000
	Fairchild Clipper	33 Mhz		2220 000
	Inmos T800		20 Mhz		4000 000
	Inmos T800		30 Mhz		6000 000

Hope this info helps a bit,


Gert Poletiek

NIKHEF-H, Dutch National Institute for Nuclear and High Energy Physics
          Kruislaan 409, P.O.Box 41882, 1009 DB Amsterdam, The Netherlands
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