🚀 go-pugleaf

[I've added comp.sys.transputer to this discussion.  For those who
haven't seen this before, someone posted rumours about an Atari
Transputer box.  Then a discussion about a Transputer's power got
started.  Inmos claims 10 MIPS, but those are Transputer MIPS, which
are about 1/2 to 1/3 of RISC MIPS, which are perhaps 1/2 of CISC MIPS.
(Using VAX 11/780 as a guide - some figures I've seen say the canonical
1 MIPS machine actually executes .5 native MIPS!)]

On the original subject:

I know Atari has wangled a deal with Inmos to get 20 MHz T414
Transputers for $50.00 (U.S.) apiece.  I also know they're paying Tim
King (the man who brought you Tripos!  Beware!) significant amounts of
money to develop Helios.  I have a preliminary spec for Helios around
here somewhere.

The current debate:

tim@amdcad.UUCP (Tim Olson) writes:
>>For example, the transputer is a stack machine.  To perform the sequence
>>
>>	a = b+c;
>>
>>(assuming a,b, and c are register variables) requires 4 instructions:
>>
>>	push b
>>	push c
>>	add
>>	pop a
>>
>>while on the 68000 it requires 2:
>>
>>	mov b, a
>>	add c, a
>>
>>and on many RISC machines it requires only 1:
>>
>>	add	a, b, c

alan@pdn.UUCP (0000-Alan Lovejoy) writes:
>That last example is a good example of a VAX-class CISC machine, not
>of any RISC machine I know of.  RISC code would probably be identical
>to the 68000 example (which is more of a RISC machine than it is given
>credit for--just wait until the 78000 is announced and you'll see what
>I mean).

Not on Tim's baby!  AMD's Am29000 uses 3-operand instructions.  So, I
might add, did the RISC II prototype chip and, I believe, the original
RISC I.

>Also, assuming that the values (a, b, c) are already in registers
>obscures the difference between RISC and 68000.  Assuming memory values
>gives:

First, Tim said "assuming register variables".  The trick is, the
Transputer hasn't got any registers in the usual sense of the word.
All it's got is a 3-word stack to evaluate expressions on (rather like
most HP calculators, only HP gives 4 words).  What the transputer
*does* have, however, is *very* fast stack-relative addressing.  The
first 16 words can be accessed using one-byte instructions, and are the
Transputer's "registers".

I have frequently wished they'd cache those 16 words.  It would
probably reduce bandwidth requirements by about 1/3, and speed up the
chip by a similar factor.

Second, One of the hallmarks of a true-blue RISC chip, however, is
*LOTS* of registers.  The Am29000, for instance, has 192.  Only large
structs and arrays need to go off-chip.

Thus, the assumption that *everything* is in a register is perfectly
valid, even in situations where other architectures would go off-chip.

>   RISC              680x0               VAX
>
>   LOAD a(FP), R0    MOVE.W a(A6), D0    ADD a(R1), b(R1), c(R1)
>   LOAD b(FP), R1    ADD.W b(A6), D0 
>   ADD R0, R1        MOVE.W D0, c(A6)
>   STORE R1, c(FP)
>  
>The RISC code will run in 4 cycles; on a 68030 with no-wait-state memory
>the 680x0 code will take at least 3 cycles but could take as many as 10 cycles 
>and will probably average 5 or 6 cycles, although that will depend on the 
>state of the instruction pipeline and on what's currently in the code and data 
>caches; I don't have enough information about the VAX instruction set to give 
>cycles--it probably is different for each VAX model anyway.

For an 11/780, it would take 1.80 microseconds (assuming a, b and c are
8-bit displacements).  0.60 microseconds if registers are being used.
Sorry, I don't know how many "cycles" that is!
--
	-Colin Plumb (watmath!ccplumb)

Zippy says:
You can't hurt me!!  I have an ASSUMABLE MORTGAGE!!