Thread View: comp.sys.celerity
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2 total messages
Started by scp Stephen C. Pope
Fri, 16 Feb 1990 16:22
Model 500 details
Author: scp Stephen C. Pope
Date: Fri, 16 Feb 1990 16:22
Date: Fri, 16 Feb 1990 16:22
43 lines
2435 bytes
2435 bytes
Someone wrote me: > Stephen, > Do you have a description of the 500 architecture > (instructions, timing, pipelines, etc.)? We have been unable to dig > one out of our local people, but we haven't pressed the issue yet. An > instruction set manual would have been very helpful in locking down > the compiler bug that zapped Perl, besides the inherent educational value. > As it is, I'm guessing at the mnemonics that I get out of the debugger. > If you have been able to get such a manual (which I presume > you'd need to port gcc), that might give us some leverage with the locals. I haven't had much more luck. All I have been able to get on this subject is a handwritten ``wall chart'' that is nearly illegible. It shows the opcode <-> mnemonic mappings, with the explaination of the mnemonic (like ``djibzm'' == ``delayed jump on indicator bit pairs zeros minus'', which is one of my favorite mind-benders). No explaination of the register set, pipelining, flags<->opcodes dependencies, or the assembler itself. Needless to say, it would be quite a chore to figure out what each of the instructions *really* does. I have it from pretty reliable sources that this little chart is all that existed about a year ago; I can't seem to get any info on any newer document. What I can't believe is that Celerity and FPS have managed to create this system without any better documentation internally. I think we'd all welcome more low level information such as this dort of stuff; it can only make the machine more usable and interesting to the world by helping us get real software running. On another note, I do wish to commend FPS on their fast response time; I mentioned the small-mindedness of their cpp a few days ago on the net, and magically a tape showed up yesterday with a bigger-tabled cpp! Thanks a million! stephen pope advanced computing lab, lanl scp@acl.lanl.gov ps. yes, I know that two copies of my postings seem to escape. Fixed Real Soon Now.
Re: Model 500 details
Author: Dan Mercer
Date: Mon, 19 Feb 1990 22:17
Date: Mon, 19 Feb 1990 22:17
46 lines
2096 bytes
2096 bytes
In article <SCP.90Feb16092214@blanche.LANL>GOV> scp@acl.lanl.gov writes: : :Someone wrote me: :> Stephen, : :> Do you have a description of the 500 architecture :> (instructions, timing, pipelines, etc.)? We have been unable to dig :> one out of our local people, but we haven't pressed the issue yet. An :> instruction set manual would have been very helpful in locking down :> the compiler bug that zapped Perl, besides the inherent educational value. :> As it is, I'm guessing at the mnemonics that I get out of the debugger. : :> If you have been able to get such a manual (which I presume :> you'd need to port gcc), that might give us some leverage with the locals. : : :I haven't had much more luck. All I have been able to get on this subject :is a handwritten ``wall chart'' that is nearly illegible. It shows the :opcode <-> mnemonic mappings, with the explaination of the mnemonic :(like ``djibzm'' == ``delayed jump on indicator bit pairs zeros minus'', :stephen pope :advanced computing lab, lanl :scp@acl.lanl.gov : :ps. yes, I know that two copies of my postings seem to escape. :Fixed Real Soon Now. I think the celerity uses the NCR/32 VLSI CPU chip. I have in my hands the _NCR/32 General Information Manual_ (c)1984 (ST-2104-23) and it does have a one page description of djibzm. I think you'll find it explains everything in adequate detail. There's an 800 number on the back: NCR VLSI Processor Products NCR Microelectronics Division Colorado Springs, Colorado (800)525-2252 Good luck! -- Dan Mercer Reply-To: mercer@ncrcce.StPaul.NCR.COM (Dan Mercer)
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