🚀 go-pugleaf

In reviewing the Technical Overview document for the DECstation
5000/240, I found several memory read latencies that were troublesome.  

	- 690 ns : single memory read from noncached address
	- 840 ns : eight word cache load (I calculated from the
				information given)
	- 320 ns : processor memory read latency
	- 440 ns : TURBOchannel memory read latency

These numbers imply that any memory access requires a 320 ns latency
probably due to a page-mode read latency.  Is this the case?  

If not, why are the latencies so large?  

If so, why is it that all reads are done using page-mode read?  

Why is the page-mode read latency 8-cycle? 

 Finally, why is the TURBOchannel latency 440 ns as opposed to 320 ns? 
(the only explaination for the 440 ns I could come up with is that this
included TURBOchannel signalling overhead, specifically cycles t1, t2,
t3(320 ns), and t4 as specified in the TURBOchannel Hardware
Specification document for DMA reads).

Too many questions?

Thanks,
Marissa Gonzalez
<mg4s@andrew.cmu.edu>