🚀 go-pugleaf

On Tue, 14 Jul 1998 22:47:26, "Ace" <listenNS@hotmail.com> wrote:

> >First of all, the cache L-number doesn't mean squat when trying to figure
> >out what's on the CPU die (K6-3), what's bonded into the ceramic package
> (as
> >with the Pentium Pro), what's integrated onto the PCB (a 'la Pentium II),
> >etc.  For an n-level cache hierarchy, the hierarchy always proceeds such
> >that *fastest* is L1 and *slowest* is Ln (you could reasonably throw in the
> >CPU registers at L0 and system RAM at Ln+1).
> 
> Actually...no. That would be an UNreasonable setup because you would check
> your slowest memory first and your fastest memory last. This is
> counterproductive to basic system design.
> 
> As a practical matter, arranging the fastest memory at L0 and the slowest at
> Ln will generally result in decreasing levels of integration with the CPU as
> you move down the cache level.

Huh?  You're going to have to explain why all system designers 
are wrong.  

The fact is that there are N-milllion transistors to spend these 
days.  An integrated L2 is a decent place to spend the buget.  

----
  Keith R. Williams
  krw@ibm.net