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Article #700

Re: Cache question..

#700
From: Hans Lindberg
Date: Wed, 24 Jan 1996 00:00
38 lines
2349 bytes
wluther@mindspring.com (J. Wade Luther) writes:

>d
>>chuckf@charm.net (Chuck Frain) writes:

>>>I
[ZAP]
>>the cache with bytes that will only be used once? Couldn't this mean that
>>the performance would depend greatly upon the number of threads/processes
>>that are running and using CPU time? In that case Win95 could possibly
>>suffer less than Win3.1 from too large cache, and WinNT even less, at
>>least when under a fair load. Just me guessing, please enlighten us
>>if you REALLY know about computers and OS internals, ANYONE.

>>Hans Lindberg, Phone: +46-31-183151 Mobile: +46-70-7813996
>>EMail: d7hansl@dtek.chalmers.se

>OK, when you have 256 K of cache you have 8 32K SRAM chips(8*32=256)
>in 2 banks, with each bank having 4 chips...when you have 512K you
>have 4 128K SRAM chips(4*128=512) in one bank...the access to the
>motherboard is faster for the 256K configuration because the
>motherboard can do bank interleaving...it can't do this with the 512K
>configuration because all the SRAM is in one bank...the end result is
>that 512K, which costs a lot more, offers only a slight increase in
>performance

Is this true for Pipelined Burrt Cache as well?


-
Hans Lindberg, Phone: +46-31-183151 Mobile: +46-70-7813996
EMail: d7hansl@dtek.chalmers.se

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From: d7hansl@dtek.chalmers.se (Hans Lindberg)
Subject: Re: Cache question..
Date: 1996/01/24
Message-ID: <4e3u6g$bhs@nyheter.chalmers.se>
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organization: Chalmers univ. of Technology
newsgroups: comp.sys.ibm.pc.hardware.chips,comp.sys.ibm.pc.hardware.misc,comp.sys.ibm.pc.hardware.systems,demon.tech.pc