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Article #43943Re: Brain-dead 286 - summary
From: Chima Echeruo
Date: Mon, 12 Mar 1990 18:22
Date: Mon, 12 Mar 1990 18:22
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1131 bytes
>In article <9982@portia.Stanford.EDU> dhinds@portia.Stanford.EDU (David Hinds) writes: >$ [...] A 20MHz 386 can still work at >$"near 0 wait states" with interleaved memory. At higher speeds, a static >$RAM cache is necessary for avoiding wait states. I don't know if there are >$cache controllers for the 286, but I'm pretty sure the Intel cache controller >$only works with 386's. My 20Mhz 286 which is based on the Chips & Tech NEAT chipset claims ZERO wait state performance using interleaved memory. Norton SI = 22.5 ------------- Chima Echeruo sl197009@silver.ucs.indiana.edu -------------------------------
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Path: arc1-ca.pugleaf.net!utzoo!attcan!uunet!tut.cis.ohio-state.edu!cica!iuvax!silver!sl197009 From: sl197009@silver.ucs.indiana.edu (Chima Echeruo) Newsgroups: comp.sys.ibm.pc Subject: Re: Brain-dead 286 - summary Message-ID: <38483@iuvax.cs.indiana.edu> Date: 12 Mar 90 18:22:49 GMT References: <8681@rosevax.Rosemount.COM> <29405@amdcad.AMD.COM> <38299@iuvax.cs.indiana.edu> <9982@portia.Stanford.EDU> <25F9E445.20494@maccs.dcss.mcmaster.ca> Sender: root@iuvax.cs.indiana.edu Distribution: na Lines: 13