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Article #1122

Re: Loading SS

#1122
From: Kirk Hays
Date: Mon, 21 Dec 1992 21:56
20 lines
1363 bytes
In article <1992Dec21.205245.13080@athena.mit.edu>, jfc@athena.mit.edu (John F Carr) writes:
|> 
|> An 80?86 disables interrupts for the instruction following a load of the SS
|> register, to allow for the stack pointer to be loaded.  What happens if the
|> following instruction faults?  Even if it doesn't reference memory, there
|> could be an instruction page fault.

External interrupts, only, are disabled - interrupts generated by the chip (aka
"internal interrupts") are always enabled.

I don't have my 386 "OS Writer's Guide" handy, but there was some discussion
about keeping certain instruction combinations from running over page boundaries.

It's a shocker to realize I was designing, writing, and testing protected mode
operating systems for the 386 eight years ago.

-- 
Kirk Hays - NRA Life.
"The only thing necessary for the triumph of evil is for good men to
do nothing."  -- Edmund Burke (1729-1797)
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Message-ID: <BzMqAJ.Gtr@SSD.intel.com>
Path: arc1-ca.pugleaf.net!sparky!uunet!gatech!destroyer!sol.ctr.columbia.edu!eff!ssd.intel.com!hays
References: <1992Dec21.205245.13080@athena.mit.edu>

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Newsgroups: comp.sys.intel
Path: arc1-ca.pugleaf.net!sparky!uunet!gatech!destroyer!sol.ctr.columbia.edu!eff!ssd.intel.com!hays
From: hays@ssd.intel.com (Kirk Hays)
Subject: Re: Loading SS
Message-ID: <BzMqAJ.Gtr@SSD.intel.com>
Sender: usenet@SSD.intel.com
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Organization: Intel Supercomputer Systems Division
References:  <1992Dec21.205245.13080@athena.mit.edu>
Date: Mon, 21 Dec 1992 21:56:43 GMT
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