🚀 go-pugleaf

>>So, are we going to see (for example) four CPUs stuffed in each corner of
>>a big die? That implies some unreasonable design choices: *four* I-caches,
>>*four* D-caches, four sets on FPUs, four sets of ALUs, etc...  No, I guess
>>looking at it like that, the idea of laying four megacells down on the
>>chip and having them communicate via test-and-set semaphores from their
>>individual caches seems slightly crazy.  It's not that there isn't enough
>>transistors to do it some day, but rather that those transistors aren't
>>being used very efficiently.
>
>       There are other ways to do it.  For example, each CPU could have a
>smallish icache and maybe dcache, and then a large section of the chip
>devoted to shared cache (either unified or split, single-ported or
>multi-ported, etc - those are details).

So whats wrong with putting one CPU on the chip and filling the rest with
DRAM? 
This might also help with the heat dissipation problem which I am told
is one of the biggest design constraints for the newer chips.
Why have lots of cool memory chips and hot CPUs, instead have lots of
luke-warm mixtures :-)
If you fill the chip with CPUs and then have to go off chip for memory
surely it is better to have the local memory close to the CPU.
You wont be able to get speedup unless each parallel CPU has a reasonably small
working set of memory anyway.
I have also wondered whether we may be reaching the point where it is better
to avoid the complexity of Superscalar etc. and just have lots of simple
CPUs with their own local memory on chip.
-- 
John Cleary
University of Calgary.
cleary@cpsc.ucalgary.ca