Article View: comp.sys.intel
Article #1281Re: Idea for the P5!
From: Samuel A. Fineberg
Date: Wed, 18 Nov 1992 22:29
Date: Wed, 18 Nov 1992 22:29
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In article <1992Nov18.203321.18612@msuinfo.cl.msu.edu>, sundaram@eecae.msu.edu writes: |> |> Hi y'all, |> |> I had a couple of ideas for how Intel could keep backward compatibility with |> its 80x86 line of processors without having to dedicate a small part of the |> P5 to emulating 80[3|4]86 code. |> |> Instead of devoting part of the die to emulate 80x86 code, why not include some |> instructions that will allow the P5 to act as a master processor to a true |> (or slightly modified) 80x86 chip. |> |> |> So, if you run a program run for the 386 on the P5, it will "make" the |> 386 execute them instead and can handle other tasks. The idea is similar |> to the DOS VDM's in IBM's OS/2. These VDM's can run most DOS 5.0 apps, |> but the "OS" they run is not DOS 5.0. Similarly, this chip will not |> quite be a true 486 but one slightly hacked to allow it to co-operate |> with the P5 and work with it as a slave processor. This MAY include |> some incompatibilities with existing software, but these can be |> virtually eliminated by intelligent design etc. Moreover, this will |> allow users to keep their old 80x86 based software while allowing them |> to step up to the P5 (or the P6, P7 .... ) and its advanced features |> and superior performance. The P5 could be sold independently, so that |> users who need x86 compsatibility can "upgrade" to it when necessary. |> Also, motherboards for the P5 could have a built in socket for the |> 486 compatible (intel) micro-(co)-processor. |> |> OK, This mirror's OS/2 2.0 's setup quite closely, where DOS/Windows |> support is optional and some programs (like WPWIN 5.1) need to be |> "fixed" before being able to run under a WINOS2 session. However, the |> setup does provide for compatibility with over 95% of the DOS software |> out there. Could this be done for the P5? |> |> |> Voila! |> |> Now, don't flame me. This is just an idea. I do not know how feasible this is |> going to be. I will let you decide. |> |> Later y'all |> |> Divya |> (sundaram@egr.msu.edu) I think the main problem is that its done. The P5 is no longer under development (though they may still be debugging it). Also, there is no P5 any more, it is called the Pentium CPU. Sure the name is stupid, but its too late to change that either. Maybe you should concentrate on the P6? Sam
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Newsgroups: comp.sys.intel Path: arc1-ca.pugleaf.net!sparky!uunet!charon.amdahl.com!pacbell.com!ames!data.nas.nasa.gov!win31.nas.nasa.gov!fineberg From: fineberg@win31.nas.nasa.gov (Samuel A. Fineberg) Subject: Re: Idea for the P5! References: <1992Nov18.203321.18612@msuinfo.cl.msu.edu> Sender: news@nas.nasa.gov (News Administrator) Organization: CSC, NASA Ames Research Center, NAS Division Date: Wed, 18 Nov 92 22:29:27 GMT Message-ID: <1992Nov18.222927.20422@nas.nasa.gov> Reply-To: fineberg@nas.nasa.gov Distribution: usa Lines: 50